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Data Sheet
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CDK1301
8-bit, 250 MSPS A/D Converter with Demuxed Outputs
features
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CDK1301 8-bit, 250 MSPS A/D Converter with Demuxed Outputs
General Description
The CDK1301 is a high-speed, 8-bit analog-to-digital converter implemented in an advanced BiCMOS process. It is a performance-enhanced version of the CDK1300, offering better linearity and dynamic performance. An advanced folding and interpolating architecture provides both a high conversion rate and very low power dissipation of only 425mW. The analog inputs can be operated in either single-ended or differential input mode. A 2.5V common mode reference is provided on chip for the single-ended input mode to minimize external components. The CDK1301 digital outputs are demuxed (double-wide) with both dualchannel and single-channel selectable output modes. Demuxed mode supports either parallel aligned or interleaved data output. The output logic is both +3.0V and +5.0V compatible. The CDK1301 is available in a 44-lead TQFP surface mount package over the industrial temperature range of -40C to +85C.
TTL/CMOS/PECL input logic compatible High conversion rate: 250 MSPS Single +5V power supply Very low power dissipation: 425mW 350MHz full power bandwidth Power-down mode: 24mW +3.0V/+5.0V (LVCMOS) digital output logic compatibility Single/demuxed output ports selectable Improved replacement for AD9054
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applications
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RGB video processing Digital communications High-speed instrumentation Digital Sampling Oscilloscopes (DSO) Projection display systems
Block Diagram
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Ordering Information
Part Number CDK1301ITQ44 CDK1301ITQ44_Q Package TQFP-44 TQFP-44 Pb-Free Yes No RoHS Compliant Yes No Operating Temperature Range -40C to +85C -40C to +85C Packaging Method Rail Rail
Moisture sensitivity level for all parts is MSL-1. (c)2008 CADEKA Microcircuits LLC www.cadeka.com
Data Sheet
Pin Configuration TQFP-44
CDK1301 8-bit, 250 MSPS A/D Converter with Demuxed Outputs
CDK1301
Pin Assignments
Pin No. 40 39 16-9 19-26 28 27 4 3 5 6 Pin Name VIN+ VINDA0-DA7 DB0-DB7 DCLKOUT DCLKOUT CLK CLK RESET RESET Description Non-inverted analog input; nominally 1Vpp; 100k pullup to Vcc and 100k pulldown to AGND, internally Inverted analog input; nominally 1Vpp; 100k pullup to Vcc and 100k pulldown to AGND, internally Data output bank A; 3V/5V LVCMOS compatible Data output bank B; 3V/5V LVCMOS compatible Non-inverted data output clock; 3v/5v 3V/5V LVCMOS compatible Inverted data output clock; 3V/5V LVCMOS compatible Non-inverted clock input pin; 100k pulldown to AGND, internally Inverted clock input pin; 17.5k pullup to Vcc and 7.5k pulldown to AGND, internally RESET synchronizes the data sampling and data output bank relationship when in dual channel mode (DMODE1 = 0); 100k pulldown to AGND, internally Inverted RESET input pin; 17.5k pullup to Vcc and 7.5 pulldown to AGND, internally Internally: 100k pulldown to AGND on DMODE1 50k pullup to Vcc on DMODE2 32, 31 DMODE1,2 Data output mode pins: DMODE1 = 0, DMODE2 = 0: parallel dual channel output DMODE1 = 0, DMODE2 = 1: interleaved dual channel output DMODE1 = 1, DMODE2 = x: single channel data output on bank a (125 MSPS max) 2 37 35, 36, 42, 43 7, 17, 30 1, 33, 34, 38, 41, 44 8, 18, 29 PD VCM AVCC OVDD AGND DGND Power-Down pin; PD = 1 for Power-Down mode. Outputs set to high impedance in Power-Down mode; 100k pulldown to AGND, internally 2.5V common mode voltage reference output +5V analog supply +3V/+5V digital output supply Analog ground Digital ground
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Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the "Absolute Maximum Ratings". The device should not be operated at these "absolute" limits. Adhere to the "Recommended Operating Conditions" for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots.
CDK1301 8-bit, 250 MSPS A/D Converter with Demuxed Outputs
Parameter Supply Voltage AVCC OVDD Input Voltages Analog inputs Digital inputs
Min
Max +6 +6
Unit V V V V
-0.5V -0.5V
Vcc +0.5V Vcc +0.5V
Reliability Information
Parameter Storage Temperature Range Min -65 Typ Max +125 Unit C
Recommended Operating Conditions
Parameter Operating Temperature Range Min -40 Typ Max +85 Unit C
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Data Sheet
Electrical Characteristics
(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, clk = 250MHz, 50% duty cycle, IN = 70MHz, dual channel mode; unless otherwise noted)
symbol parameter
Resolution
conditions
Min
typ
8
Max
units
bits
CDK1301 8-bit, 250 MSPS A/D Converter with Demuxed Outputs
DC Performance
DLE ILE Differential Linearity Error Integral Linearity Error No Missing Codes +25C, IN = 1KHz(1) -40C to +85C, IN = 1KHz +25C, IN = 1KHz(1) -40C to +85C, IN = 1KHz(2) @250 MSPS, IN = 1KHz with respect to VIN2.0 +25C +25C +25C +25C (-3dB of FS) +25C +25C AVcc = 5V 0.25V 25
(2) (1) (2)
-0.68 -0.95
0.4 0.7 1.2 1.4
0.68 0.95 1.90 2.15
LSB LSB LSB LSB
Guaranteed 512 2.5 13 50 5 350 -7.5 -5 <1 250 8 16 0.3 2.0 2.5 2.5 2.5 3.5 5.0 5.6 5.18 5.73 18.1 5.3 5.9 9.4 +3.5 +5 3.0 mVpp V A k pF MHz %FS LSB LSB MSPS ns ps/C ns ps-RMS Cycle Cycle Cycle Cycle ns ns ps/C Bits Bits dB dB -41.5 -40.3 dB dB dB dB
Analog Input
Input Voltage Range VCM Input Common Mod Input Bias Current Input Resistance Input Capacitance Input Bandwidth Gain Error(1) Offset Error PSRR
(1) (2)
Offset Power Supply Rejection Ratio Conversion Rate(2)
Timing Characteristics
tpd1 tap Output Delay (Clock-to-Data) Output Delay Tempco Aperture Delay Time Aperture Jitter Time Pipeline Delay (Latency) Single Channel Mode Demuxed Interleaved Mode Demuxed Parallel Mode Channel B Channel A CLK to DCLKOUT Delay Time tpd2 tpd3 Single Channel Mode(2) Dual Channel Mode
(2)
-40C to +85C
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Output Delay (Clock to DClock)
Dynamic Performance
ENOB SNR THD SINAD
notes: 1. 100% production tested at +25C. 2. Parameter is guaranteed (but not tested) by design and characterization data.
Effective Number of Bits Signal-to-Noise Ratio Total Harmonic Distortion Signal-to-Noise and Distortion
IN = 70MHz, +25C(1) IN = 70MHz, -40C to +85C(2) IN = 70MHz,+25C(1) IN = 70MHz, -40C to +85C IN = 70MHz, +25C(1) IN = 70MHz, -40C to +85C(2) IN = 70MHz, +25C
(1) (2)
6.4 6.25 44.3 42.6
7.0 6.8 46.1 45.4 -47 -45.5
40.2 39.3
43.7 42.8
IN = 70MHz, -40C to +85C(2)
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Data Sheet
Electrical Characteristics
(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, clk = 250MHz, 50% duty cycle, IN = 70MHz, dual channel mode; unless otherwise noted)
symbol
AVcc OVDD AIcc OIDD
parameter
Analog Voltage Supply(2) Digital Voltage Supply(2) Current Current Single Mode Parallel Mode Interleave Mode Power Dissipation Voltage(1) Voltage Tempcp Open Impedance
(1) (1)
conditions
Min
4.75 2.75
typ
5.0 85
Max
5.25 5.25 110 5.5
units
Power Supply Requirements
CDK1301 8-bit, 250 MSPS A/D Converter with Demuxed Outputs
V V mA mA mA mA mA
Current Power-down(1)
+25C OVDD = 3.0V, 10pF load
4.8 35 55 55 425 2.44 2.5 84 1.07 47.5 400 1.4 0
550 2.56
mW V ppm/C k mV/V mVpp
Common Mode Reference Output
IOUT = 50A
PSRR VDIFF VIHD VILD VCMD VIH VIL IIH IIL
Power Supply Rejection Ratio Differental Signal Amplitude(2) Differental High Input Voltage(2) Differental Low Input Voltage(2) Differental Common Mode Input
(2)
Clock and Reset Inputs (Differential and Single-Ended)
AVcc 3.9 4.1 1.2 43 43 +100 +100 AVcc 1.0 0.5 50 +100 +100 V V V V V A A V V A A V 0.2 3.3/3.0 2.3/1.9 1.2/1.0 0.7/0.6 V ns ns ns ns
1.2 1.8 0 VID = 1.5V VID = 1.5V -100 -100 2.0 0 -100 -100 IOH = -0.5mA IOL = +1.6mA OVDD = 3V, 10pF load OVDD = 5V, 10pF load OVDD = 3V, 10pF load OVDD = 5V, 10pF load OVDD-2.0
Single-Ended High Input Voltage(1) Single-Ended Low Input Voltage(2) High Input Current
(1)
Low Input Current(1) High Input Voltage(2) Low Input Voltage(2) Max Input Current Low(1) Max Input Current High <4.0V(1)
Power Down and Mode Control Inputs (Single-Ended)
Digital Outputs
Logic "1" Voltage(1) Logic "0" Voltage TR/TF Data TR/TF DCLK
notes: 1. 100% production tested at +25C. 2. Parameter is guaranteed (but not tested) by design and characterization data.
(1)
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Data Sheet
Typical Performance Characteristics
(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, clk = 250MHz, 50% duty cycle, IN = 70MHz, dual channel mode; unless otherwise noted) DLE vs. Sample Rate
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7
IN = 70.1 MHz
DLE vs. Temperature
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7
CDK1301 8-bit, 250 MSPS A/D Converter with Demuxed Outputs
IN = 70.1MHz S = 250 MSPS
LSB
LSB
200
225
250
260
-50
-25
0
25
50
75
100
Sample Rate (MSPS)
Temperature (C)
DLE vs. AVcc
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 100
IN = 70.1MHz S = 250 MSPS
AVcc Current vs. Temperature
90 80 70 60 50 40 30 20 10
Powerdown mode
IN = 70.1MHz S = 250 MSPS
AVCC Current (mA)
LSB
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
0
-50
-25
0
25
50
75
100
Volts (V)
Temperature (C)
SNR, SINAD vs. Sample Rate
60 55
IN = 70.1 MHz
SNR SINAD
SFDR, THD vs. Sample Rate
-30 -35
IN = 70.1 MHz
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SNR, SINAD (dB)
SFDR, THD (dB)
50 45 40 35 30 25 20 200 225
-40 -45 -50 -55 -60 -65
THD SFDR
250
260
-70 200 225 250 260
Sample Rate (MSPS)
Sample Rate (MSPS)
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Data Sheet
Typical Performance Characteristics
(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, clk = 250MHz, 50% duty cycle, IN = 70MHz, dual channel mode; unless otherwise noted) SNR, SINAD vs. Temperature
60 55
IN = 70.1 MHz S = 250 MSPS SNR SINAD
THD vs. Temperature
-30
CDK1301 8-bit, 250 MSPS A/D Converter with Demuxed Outputs
-35 -40
SNR, SINAD (dB)
50 45 40 35 30 25 20 -50 -25 0 25 50
IN = 70.1 MHz S = 250 MSPS
THD (dB)
75 100
-45 -50 -55 -60 -65 -70 -50 -25 0 25 50 75 100
Temperature (C)
Temperature (C)
SNR, SINAD vs. Duty Cycle
60 55
IN = 70.1 MHz S = 250 MSPS
SNR SINAD
SFDR, THD vs. Duty Cycle
-30 -35
IN = 70.1 MHz S = 250 MSPS
SNR, SINAD (dB)
SFDR, THD (dB)
50 45 40 35 30 25 20 35 40 45 50
-40 -45 -50 -55 -60 -65
THD SFDR
55
60
-70
35
40
45
50
55
60
Duty Cycle (%)
Duty Cycle (%)
SNR, SINAD vs. AVcc
60 55
IN = 70.1 MHz S = 250 MSPS
SNR SINAD
THD vs. AVCC
-30 -35 -40
IN = 70.1 MHz S = 250 MSPS
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SNR, SINAD (dB)
50 45 40 35 30 25 20
THD (dB)
-45 -50 -55 -60 -65
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
-70
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
Volts (V)
Volts (V)
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Data Sheet
Theory of Operation
The CDK1301 is a three-step subranger. It consists of two THAs in series at the input, followed by three ADC blocks. The first block is a three-bit folder with over/under range detection. The second block consists of two singlebit folding interpolator stages. There are pipelining THAs between each ADC block. The analog decode functions are the input buffer, input THAs, three-bit folder, folding interpolators, and pipelining THAs. The input buffer enables the part to withstand railto-rail input signals without latchup or excessive currents and also performs single-ended to differential conversion. All of the THAs have the same basic architecture. Each has a differential pair buffer followed by switched emitter followers driving the hold capacitors. The input THA also has hold mode feedthrough cancellation devices. The three MSBs of the ADC are generated in the first threebit folder block, the output of which drives a differential reference ladder which also sets the full-scale input range. Differential pairs at the ladder taps generate midscale, quarter and three-quarter scale, overrange, and underrange. Every other differential pair collector is cross-coupled to generate the eighth scale zero crossings. The middle ADC block generates two bits from the folded signals of the previous stages after pipeline THAs. Its outputs drive more pipeline THAs to push the decoding of the three LSBs to the next half clock cycle. The three LSBs are generated in interpolators that are latched one full clock cycle after the MSBs. The digital decode consists of comparators, exclusive of
cells for gray to binary decoding, and/or cells used for mostly over/under range logic. There is a total of 2.5 clock cycles latency before the output bank selection. In order to reduce sparkle codes and maintain sample rate, no more than three bits at a time are decoded in any half clock cycle. The output data mode is controlled by the state of the demux mode inputs. There are three output modes:
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CDK1301 8-bit, 250 MSPS A/D Converter with Demuxed Outputs
All data on bank A with clock rate limited to one-half maximum Interleaved mode with data alternately on banks A and B on alternate clock cycles Parallel mode with bank A delayed one cycle to be synchronous with bank B every other clock cycle
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If necessary, the input clock is divided by two. The divided clock selects the correct output bank. The user can synchronize with the divided clock to select the desired output bank via the differential RESET input. The output logic family is CMOS with output OVDD supply adjustable from 2.7V to 5.25V. There are also differential clock output pins that can be used to latch the output data in single bank mode or to indicate the current output bank in demux mode. Finally, a power-down mode is available, which causes the outputs to become tri-state, and overall power is reduced to about 24mW. There is a 2V reference to supply common mode for single-ended inputs that is not shut down in powerdown mode.
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Figure 1. Single Mode Timing Diagram
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Data Sheet
CDK1301 8-bit, 250 MSPS A/D Converter with Demuxed Outputs
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Figure 2. Dual Mode Timing Diagram
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Data Sheet
CDK1301 8-bit, 250 MSPS A/D Converter with Demuxed Outputs
CDK1301
Figure 3. Typical Interface Circuit
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Figure 4. CLK and Reset Equivalent Circuit (without ESD Diodes)
Figure 5. Analog Input Equivalent Circuit
Typical Interface Circuit
Very few external components are required to achieve the stated device performance. Figure 3 shows the typical interface requirements when using the CDK1301 in normal circuit operation. The following sections provide descriptions of the major functions and outline performance criteria to consider for achieving the optimal device performance.
Analog Input
The input of the CDK1301 can be configured in various ways depending on whether a single-ended or differential input is desired. The AC-coupled input is most conveniently implemented using a transformer with a center-tapped secondary winding. The center tap is connected to the VCM pin as shown in Figure 3. To obtain low distortion, it is important that the
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Data Sheet
selected transformer does not exhibit core saturation at the full-scale voltage. Proper termination of the input is important for input signal purity. A small capacitor across the input attenuates kickback noise from the internal trackand-hold. Figure 6 illustrates a solution (based on operational amplifiers) that can be used if a DC-coupled single-ended input is desired.
Common-Mode Voltage Reference Circuit
The CDK1301 has an on-board common-mode voltage reference circuit (VCM). It is 2.5V and is capable of driving 50A loads typically. The circuit is commonly used to drive the center tap of the RF transformer in fully differential applications. For single-ended applications, this output can be used to provide the level shifting required for the single-to-differential converter conversion circuit. Bypass VCM to AGND by external 0.01F capacitor, as shown in Figure 3 on the previous page.
CDK1301 8-bit, 250 MSPS A/D Converter with Demuxed Outputs
Clock Input
The clock input on the CDK1301 can be driven by either a single-ended or double-ended clock circuit and can handle TTL, PECL, and CMOS signals. When operating at high sample rates it is important to keep the pulse width of the clock signal as close to 50% as possible. For TTL/ CMOS single- ended clock inputs, the rise time of the signal also becomes an important consideration. Figure 6. DC-Coupled Single-Ended to Differential Conversion (power supplies and bypassing are not shown)
Digital Outputs
The output circuitry of the CDK1301 has been designed to be able to support three separate output modes. The demuxed (double-wide) mode supports either parallel aligned or interleaved data output. The single-channel mode is not demuxed and can support direct output at speeds up to 125 MSPS. The output format is straight binary (Table 1). Table 1. Output Data Format
analog input +FS +FS - 1 LSB +1 FS -FS + 1 LSB -FS
O indicates the flickering bit between logic 0 and 1
Input Protection
All I/O pads are protected with an on-chip protection circuit. This circuit provides ESD robustness and prevents latchup under severe discharge conditions without degrading analog transmission times.
Power Supplies and Grounding
The CDK1301 is operated from a single power supply in the range of 4.75V to 5.25V. Normal operation is suggested to be 5.0V. All power supply pins should be bypassed as close to the package as possible. The analog and digital grounds should be connected together with a ferrite bead as shown in the typical interface circuit and as close to the ADC as possible.
output code D7-D0 1111 1111 1111 111O 1000 000O 0000 000O 0000 0000
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Power-Down Mode
To save on power, the CDK1301 incorporates a powerdown function. This function is controlled by the signal on pin PD. When pin PD is set high, the CDK1301 enters the power-down mode. All outputs are set to high impedance. In the powerdown mode the CDK1301 dissipates 24mW typically.
The data output mode is set using the DMODE1 and DMODE2 inputs (pins 32 & 31 respectively). Table 2 describes the mode switching options. Table 2. Output Data Modes
output Mode Parallel Dual Channel Output Interleaved Dual Channel Output Single Channel Data Output (Bank A only 125 MSPS max) DMoDe1 0 0 1 DMoDe2 0 1 X
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Data Sheet
Evaluation Board
The TBD evaluation board is available to aid designers in demonstrating the full performance of the CDK1301. This board includes a clock driver and reset circuit, adjustable references and common mode, a single-ended to differential input buffer and a single-ended to differential transformer (1:1). An application note (TBD) describing the operation of this board, as well as information on the testing of the CDK1301, is also available. Contact the factory for price and availability of the TBD.
CDK1301 8-bit, 250 MSPS A/D Converter with Demuxed Outputs
Mechanical Dimensions
TQFP-44 Package
A B SYMBOL A B C D E F G H I J K MIN
TQFP-44
INCHES TYP 0.472 0.394 0.394 0.472 0.031 MAX MILLIMETERS MIN TYP MAX 12.00 10.00 10.00 12.00 0.80 0.45 1.45 0.15 0.75 1.00 0-7
PIN1
Index
CD
0.012 0.053 0.002 0.018 0.039 0-7
0.018 0.057 0.006 0.030
0.300 1.35 0.05 0.45
E
F
G H
I
K
J
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caDeKa Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free)
CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright (c)2008 by CADEKA Microcircuits LLC. All rights reserved.
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